Devices and methods including an etch stop protection material

ABSTRACT

Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.

PRIORITY APPLICATION

This application is a continuation of U.S. application Ser. No.15/470,617, filed Mar. 27, 2017, which is a divisional of U.S.application Ser. No. 14/722,824, filed May 27, 2015, all of which areincorporated herein by reference in their entirety.

BACKGROUND

Some memory cells may include a dielectric between a control gate (CG)and a nitride structure. The dielectric may include an oxide. A floatinggate (FG) may be separated from the nitride structure by anotherdielectric. The nitride structure may be wrapped around three sides ofthe FG. Charges may become undesirably trapped in the nitride structure,particularly in portions of the nitride structure that are not directlybetween the CG and the FG. The threshold voltage (V_(t)) of a cell maybe altered by the trapped charges in the nitride structure. In adielectric (e.g., nitride material or other dielectric) removal process,an etch stop material of a memory may be negatively affected.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates, by way of example, a block diagram of an embodimentof a first material situated to protect a second material.

FIG. 1B illustrates, by way of example, a block diagram of anotherembodiment of a first material situated to protect a second material.

FIGS. 2A and 2B illustrate cross-section views of examples of a verticalthree-dimensional memory.

FIGS. 3A-3K illustrate, by way of example, block diagrams of anembodiment of a technique of making a vertical memory.

FIGS. 4A-4E illustrate, by way of example, block diagram of anotherembodiment of a technique of making a vertical memory.

DESCRIPTION OF THE EMBODIMENTS

The following detailed description refers to the accompanying drawingswhich show, by way of illustration, specific aspects and embodiments inwhich the present subject matter may be practiced. These embodiments aredescribed in sufficient detail to enable those skilled in the art topractice the present subject matter.

The term “horizontal” as used in this application is defined as a planeparallel to the conventional plane or surface of a wafer, such as asubstrate, regardless of the actual orientation of the wafer orsubstrate. The term “vertical” refers to a direction perpendicular tothe horizontal as defined above. Prepositions, such as “on”, “side”.“higher”, “lower”, “over” and “under” are defined with respect to theconventional plane or surface being on the top surface of the wafer orsubstrate, regardless of the actual orientation of the wafer orsubstrate. The terms “wafer” and “substrate” are used herein to refergenerally to any structure on which integrated circuits are formed, andalso to such structures during various stages of integrated circuitfabrication. The following detailed description is, therefore, not to betaken in a limiting sense, and the scope of the present invention isdefined only by the appended claims, along with the full scope ofequivalents to which such claims are entitled.

A dielectric may be formed by a deposition (e.g., a conformaldeposition) of a polysilicon (e.g., a thin film) and a subsequentoxidation that at least partially converts the polysilicon structureinto an oxide (i.e. an oxidized polysilicon). The oxidized polysiliconstructure may be formed on another material (e.g., a metal oxide, suchas aluminum oxide, zirconium oxide, hafnium oxide, silver oxide, ironoxide, chromium oxide, titanium oxide, copper oxide, zinc oxide, or thelike). An In Situ Steam Generation (ISSG) oxidation process mayselectively oxidize exposed polysilicon. The oxidized polysilicon may beused as an etch barrier for a material covered by the oxidizedpolysilicon (e.g., a metal oxide). Such an oxidized polysilicon mayprotect a material that is susceptible to chemical interaction or damagefrom a downstream process. For example, the oxidized polysilicon mayprotect a metal oxide etch stop material from a hot phosphoric acid orother chemical, mechanical, or electrical removal process that is usedto remove a material (e.g., a nitride material) situated on the oxidizedpolysilicon.

For a NAND memory, one or more embodiments of the disclosure may helpreduce a problem associated with a chemical selectivity between anitride material and an etch stop material (e.g., a metal oxide). One ormore embodiments may provide a method of removing a nitride materialfrom a sidewall of a trench without damaging an etch stop material. Thenitride material may otherwise be a source of trapped charge in thechannel or control gate recesses and may contribute to a reduced chargedensity (CD).

Generally, the devices and techniques are applicable to a situation inwhich a selective etch process may damage a first material, but does notinteract with or damage a second material. In such a situation, thesecond material may be situated on the first material, the selectiveetch process may be performed, and the second material may help protectthe first material from interacting with or being damaged by theselective etch process. The second material may be oxidized prior toperforming the second etch process.

One category of devices that may benefit from such a protective materialincludes a vertical three-dimensional (3D) memory, such as that shown inFIGS. 3A-3K and FIGS. 4A-4E. In one or more embodiments, a 3D memory mayinclude a memory stack. A memory stack may include a stack of at leasttwo memory cells and a tier dielectric between adjacent memory cells,where each memory cell includes a control gate (CG) and a charge storagestructure, such as a floating gate (FG) or charge trap (CT), configuredto store electrons or holes accumulated thereon. Information isrepresented by the amount of electrons or holes stored by the cell. Thememory stack may further include an inter-gate dielectric (IGD)comprising a composite of oxide-nitride-oxide (“ONO”), where the IGD maybe between the charge storage structure and the CG. The nitride materialand the charge storage structure may be laterally positioned adjacent,and/or horizontally aligned to each other, or have substantially equalheights. One or more of the oxides in the IGD may be an oxidizedpolysilicon, in one or more embodiments. The IGD may sometimes bereferred to as an inter-poly dielectric (IPD), such as in an embodimentwhere the CG and the FG each include a polysilicon material.

A NAND array architecture is an array of memory cells arranged such thatthe memory cells of the array are coupled in logical rows to accesslines (which are coupled to, and in some cases are at least partiallyformed by, the CGs of the memory cells), which are conventionallyreferred to as word lines. Some memory cells of the array are coupledtogether in series between a source and the data line, which isconventionally referred to as a bit line.

Memory cells in NAND array architecture may be programmed to a desireddata state. For example, electric charge may be accumulated (e.g.,placed) on, or removed from, an FG of a memory cell to program the cellinto a desired one of a number of data states. A memory cellconventionally referred to as a single level cell (SLC) may beprogrammed to a desired one of two data states, e.g., a “1” or a “0”state. Memory cells conventionally referred to as multilevel cells(MLCs) may be programmed to a desired one of more than two data states.

The V_(t) of the cell may be modified by storing electrons on the FG.Thus, when the cell is “read” by placing a specific voltage on the CG(e.g., by driving the access line coupled to the cell with a readvoltage), electrical current will either flow or not flow in the cell'schannel depending on the V_(t) of the cell and the specific voltageplaced on the CG. This presence or absence of current may be sensed andtranslated into 1's and 0's, reproducing the stored data.

Each memory cell may not directly couple to a source and a data line.Instead, the memory cells of an example array may be arranged togetherin strings, typically of 4, 8, 16, 32, or more cells each, where thememory cells in the string are coupled together in series between acommon source and a data line.

A NAND array may be accessed by a row decoder activating a row of memorycells by driving the access line coupled to those cells with a voltage.In addition, the access lines coupled to the unselected memory cells ofeach string may be driven with a different voltage. For example, theunselected memory cells of each string may be driven with a pass voltageso as to operate them as pass transistors, allowing them to pass currentin a manner that is unrestricted by their programmed data states.Current may then flow from the source to the data line through eachmemory cell of the series coupled string, restricted by the memory cellof each string that is selected to be read. This places the currentlyencoded, stored data values of the row of selected memory cells on thedata lines. A page of data lines is selected and sensed, and thenindividual data words may be selected from the sensed data words fromthe page and communicated from the memory apparatus.

The flash memory, such as a NAND array, may be formed as a 3D memorywith stacks of more than one memory cells. The CGs for the memory cellsmay be adjacent to CG recesses.

FIG. 1A shows a block diagram an example of a portion of a device 100A,in accord with one or more embodiments. The device 100A may include aprotective material 102 and a protected material 104. The protectedmaterial 104 may be protected from a chemical process, mechanicalprocess, electrical process, or a combination thereof, by the protectivematerial 102. The protective material 102 may include an electrical,mechanical, or chemical property that makes it resistant to or immunefrom a process that may harm or alter the protected material 104.

FIG. 1B shows a block diagram of an example of a portion of a device100B, in accord with one or more embodiments. The portion of the device100B may include an oxidized polysilicon 110 on a metal oxide 106. Theoxidized polysilicon 110 may include a polysilicon that is at leastpartially converted to an oxide, such as by performing an ISSG processon the polysilicon. The polysilicon may be deposited (e.g., using aconformal deposition process) on the metal oxide 106 prior to performingthe ISSG process. The oxidized polysilicon 110 may protect the metaloxide from a hot phosphorous etch process or other selective chemicalprocess that may damage or otherwise alter the metal oxide 106.

FIG. 2A shows a cross-section view of an example of a verticalthree-dimensional memory 200A. FIG. 2A shows a first CG 206A, 206B overan etch stop material 222, a first tier dielectric 224A, 224B over thefirst CG 206A-B, a second CG 206C, 206D over the first tier dielectric224A-B, a second tier dielectric 224C, 224D over the second CG 206C-D,and a mask material (e.g., dielectric, such as oxide, nitride, orpolysilicon) 226 over the second tier dielectric 224C-D. The memory 200Amay include an oxide 208 situated in a control gate recess 230. Theoxide 208 may be grown on the CG using an ISSG process. A CG recess 230may include a height dimension 252. A trench 228 may include a widthdimension 250.

FIG. 2B shows a cross-section view of an example of a verticalthree-dimensional memory 200B. The memory 200B may be similar to thememory 200A with the memory 200B including a nitride material 232 onsidewalls of the trench 228 and in the CG recesses 230. A process toremove the nitride material 232 from the trench 228 and leave thenitride material 232 only in the CG recesses 230 may damage an etch stopmaterial 222, thus making it difficult to remove the nitride material232 from the trench 228. The process of removing the nitride material232 may also damage other items of FIGS. 2A and 2B, such as the maskmaterial 226, or the tier dielectric 224A-D.

FIG. 3A-K shows a cross-section view of process steps of an example of atechnique of making a device 300, such as a vertical NAND memory. Thetechnique as shown in FIGS. 3A-3K includes a protective material (e.g.,an at least partially oxidized polysilicon 310 as shown in the processof FIGS. 3C-3K) protecting a material (e.g., an etch stop material 322,such as a metal oxide, as shown in FIGS. 3A-3 k) from a downstreamprocess (e.g., a hot phosphoric acid removal process or another processmentioned with regard to FIGS. 3D-3K). Note that the notation “300” isused herein to refer generally to the result of a process that mayinclude intermediate devices 300A, 300B, 300C, 300D, 300E, 300F, 300G,300H, 300I, 300J, and/or 300K.

FIG. 3A shows a device 300A including an etch stop material 322 over asource 305, a polysilicon material 301 over the etch stop material 322,and a first tier dielectric 303 over the polysilicon material 301. Thedevice 300A as illustrated includes a first CG 306A, 306B over the tierdielectric 303, a second tier dielectric 324A, 324B over the first CG306A-B, a second CG 306C. 306D over the tier dielectric 324A-B, a thirdtier dielectric 324C, 324D over the second CG 306C-D. and a maskmaterial (e.g., dielectric, such as oxide, nitride, or polysilicon) 326over the second tier dielectric 324C-D. The device 300A may include atrench 328 and a plurality of CG recesses 330. The polysilicon material301 can operate as a select gate source (SGS) for the device.

A polysilicon 308, may be formed on the sidewalls of the trench 328 andon exposed surfaces of the CGs 306A-D in the CG recesses 330, such asshown in the device 300B of FIG. 3B. The CG recesses 330 may be gaps(filled or unfilled) between tier dielectrics 324 adjacent to the CGs306A-D formed between the tier dielectrics 324A-D.

The polysilicon 308 may reduce one or more dimensions of the device 300Bas compared to the device 200A. For example, the CG recesses 330 mayinclude a height dimension 352 that is smaller than the height dimension252 of the CG recesses 230. The width dimension 350 of the trench 328may be smaller than the width dimension 250 of the trench 228.

The polysilicon 308 may be at least partially oxidized and converted toan oxidized polysilicon 310, such as shown in device 300C of FIG. 3C.The polysilicon 308 may be converted to the oxidized polysilicon 310 byusing an ISSG process. The ISSG process is a selective process thatoxidizes exposed polysilicon, such as the polysilicon 308, but does notoxidize the CG 306A-D, the etch stop material 322, the tier dielectric303, 324A-D, and/or the mask material 326. The oxidized polysilicon 310may help protect the etch stop material 322 from a downstream process,such as a dielectric material removal process that may chemicallyinteract with the etch stop material 322 and change or damage the etchstop material 322.

The trench 328 and the CG recesses 330 may be at least partially filledwith a nitride material 332, such as shown in the device 300D of FIG.3D. The nitride material 332 may be deposited or otherwise formed in thetrench 328 and CG recesses 330. The nitride material 332 may bepartially removed, such as by using a mechanical, chemical, laser,vapor, or photo etching process. The nitride material 332 may bepartially removed from the trench 328 and CG recesses 330 to leave atleast some of the nitride material 332 in the CG recesses 330 to form anitride structure 304 adjacent to the CGs 306, such as shown in thedevice 300E of FIG. 3E. Each nitride structure 304 in a respective CG330 may be electrically isolated from the other nitride structures 304.The nitride material 332 may be removed using hot phosphoric acid. Thesize or shape of the nitride material 332 remaining after the processmay be controlled by using hot phosphoric acid at different temperaturesor concentrations, or by exposing the nitride material 332 to the hotphosphoric acid for varying amounts of time. The oxidized polysilicon310 may help protect the etch stop material 322 from the hot phosphoricacid or other process used to remove nitride material 332.

A dielectric 312 (which may or may not be substantially the samedielectric material as the oxidized polysilicon 310 or the polysilicon308, as shown in FIGS. 3C and 3B, respectively) may be formed, such asby growing the dielectric 312 using an ISSG process, on the nitridestructures 304, such as shown in the device 300F of FIG. 3F.

The trench 328 and the CG recesses 330 may be at least partially filledwith a charge storage material 334, such as shown in device 300G of FIG.3G. The charge storage material 334 may be conductively dopedpolysilicon. The charge storage material 334 may be deposited to atleast partially fill the CG recesses 330. The charge storage material334 may be at least partially removed to form the FGs 302, such as shownin the device 300H of FIG. 3H. The charge storage material 334 may be atleast partially removed from the trench 328 and CG recesses 330, andremaining portions of the charge storage material 334 may be left in theCG recesses 330, such as to form the FGs 302.

The portions of charge storage material 334 may be removed using aCertas™ (e.g., a vapor ammonia), an ammonium fluoride and nitric acidmix (NH4F—HNO3), an ozone (O3) or hydrofluoric acid (HF) mix or cycle(e.g., exposed surfaces may be exposed to ozone to create oxide (e.g.,oxidize) the surface and the oxidized surface may be exposed tohydrofluoric acid to remove the oxide), hydrofluoric acid and nitricacid mix (HF—HNO3), hydrofluoric acid and hydrogen peroxide mix(HF—H2O2), or a tetra methyl ammonium hydroxide (TMAH) process. Theprocess used to remove portions of charge storage material 334 may be afunction of the doping of the charge storage material 334. For example,if the charge storage material 334 is n-type polysilicon, the TMAHprocess may be used to remove the portions of charge storage material334.

A dielectric 314, such as a tunnel oxide, may be formed (e.g., grownusing an ISSG process) on the FGs 302, such as shown on device 300I ofFIG. 3I. One or more polysilicon liners 307 may be deposited, so as toconform to an outline of and at least partially fill the trench 328. Adevice 300J including the polysilicon liner(s) 307 is shown in FIG. 3J.The polysilicon liner 307 can be formed on exposed surfaces of thetrench 328, such as the sidewalls of the trench 328. The liner 307 mayprotect or shield the oxidized polysilicon 310 and/or the dielectric 314from a downstream process. The device 300K of FIG. 3K shows the device300J after a punch (e.g., a dry etch) through the bottom of the trench328 and to the source 305 (e.g., a polysilicon material) has been formedand at least partially filled with a channel material 316. Thepolysilicon liner 307 and/or oxidized polysilicon 310 in the bottom ofthe trench 328, and a portion of the etch stop material 322 may bepunched through or otherwise removed, such as to allow electricalcontact to the source 305 (e.g., through the channel material 316).

The CG 306, polysilicon 308, dielectric 312, charge storage material334, and/or nitride material 332 may be deposited (e.g., conformallydeposited) using a Plasma Enhanced Chemical Vapor Deposition (PECVD)process.

FIGS. 4A-4E show an example of a technique of making a device 400. Notethat the notation “400” is used herein to refer generally to the resultof a process that may include intermediate devices 400A. 400B, 400C,400D, and/or 400E. The technique as shown in FIGS. 4A-4E includes an atleast partially oxidized polysilicon protecting an etch stop material(e.g., a metal oxide) from a downstream process (e.g., a hot phosphoricacid removal process or another process mentioned with regard to FIGS.4B-4E).

The device 400A in FIG. 4A may be substantially similar to the device300C shown in FIG. 3C with a nitride material 332 deposited (e.g.,conformally deposited) on the oxidized polysilicon 310. A sacrificialmaterial 432 may be deposited in the trench 328, such as shown in device400B of FIG. 4B. The sacrificial material 432 may be deposited orotherwise formed on the nitride material 332 in the trench 328 and CGrecesses 330. The sacrificial material 432 may be deposited using anAtomic Layer Deposition (ALD) process, High Aspect Ratio Process (HARP),or other process. The sacrificial material 432 may be a polysilicon,oxide, Tetraethyl Orthosilicate (TEOS), an organic, such as carbonBottom Anti-Reflective Coating (BARC) or resist, nitride, doped versionsthereof, or combinations thereof. The sacrificial material 432 may beuseful in techniques where a downstream process, such as phosphoric acidnitride material removal, may damage the material that would otherwisebecome an FG 302 if the sacrificial material 432 were not used. Thesacrificial material 432 may be at least partially removed from thetrench 328, leaving some sacrificial material 432 in the CG recesses330, such as shown in the device 400C of FIG. 4C. In embodiments inwhich the sacrificial material 432 comprises polysilicon a TMAH, ammonia(NH4OH), or vapor ammonia process may be used to at least partiallyremove the sacrificial material 432. When the sacrificial material 432comprises an oxide or nitride deposited by means of an ALD or otherprocess, hydrofluoric acid or hot phosphoric acid may be used to atleast partially remove the sacrificial material 432. When thesacrificial material 432 comprises TEOS or a HARP material hydrofluoricacid may be used to at least partially remove the sacrificial material432. When the sacrificial material comprises BARC or resist ananisotropic dry etch or plasma dry strip (e.g., “descum”) may be used toat least partially remove the sacrificial material 432.

As shown in device 400D of FIG. 4D, portions of the nitride material 332may be removed, such as by using hydrofluoric acid, from the sidewallsof the trench 328 and portions of exposed surfaces of the CG recesses330. The nitride material 332 may be etched to at least partially removethe nitride material 332 from the trench 328 and the CG recesses 330. Asshown in the device 400D of FIG. 4D, the etching may form a nitridestructure 304 adjacent to the oxidized polysilicon 310 in a respectiveCG recess 330. The sacrificial material 432 may be resistant to aremoval process such as to be protected from the removal process used toremove the nitride material 332. The removal process may include achemical etch that includes a chemical, such as hot phosphoric acid,that selectively removes portions of the nitride material 332 and doesnot remove or interact with the oxidized polysilicon 310. The oxidizedpolysilicon 310 may help protect the etch stop material 322 from beingdamaged or otherwise altered by the etching or removal of the nitridematerial 332. The sacrificial material 432 may be removed, such as shownin device 400E FIG. 4E. The device 400E of FIG. 4E is substantiallysimilar to the device 300E of FIG. 3E, with the device 400E formed by adifferent process than the device 300E. The device 400E can be processedin the same manner as the device 300E, such as to produce the device300K of FIG. 3K (by following the steps depicted and described withregard to FIG. 3F-3K).

One or more embodiments discussed herein may provide an alternative tousing an expensive chemical process or using a hafnium oxide (HfOx)material. Using an oxidized polysilicon may help provide a physicalbarrier to protect an etch stop material (e.g., a metal oxide) from adownstream process. One or more embodiments discussed herein may providea generally planar nitride structure 304, as compared to a nitridestructure that surrounds an FG on three sides.

A problem associated with memory cells that include a nitride adjacentto an FG on more than one side may be charges getting trapped inportions of the nitride that do not separate the FG and a CG (e.g., inportions of the nitride that are not directly between the FG and theCG). Also, trapped charge may migrate along the IGD, such as throughprogram, erase, or temperature cycling. Such charge trapping or movementmay alter the threshold voltage (V_(t)) of the memory cell or degradeincremental step pulse programming (ISPP) relative to memory cells thatdo not have such charge trapping in the nitride.

Such charge trapping or migration on the nitride may be at leastpartially eliminated by including nitride adjacent to only one surfaceof the FG (e.g., by including nitride that is substantially rectangularand not “U” shaped). Such a configuration may include charge beingtrapped on the FG rather than on the nitride.

An advantage of one or more embodiments may include reducing theincidents of erase saturation in memory cells. Another advantage mayinclude improved alignment between the FG and CG due to eliminating asource of variation in manufacturing, such as the nitride wrapping inirregular shapes around corners in a CG recess or a tier oxide. Insteadthe FG shape and size may be defined by a plasma enhanced chemical vapordeposition (PECVD) process, which may be a substantially uniform stackdeposition process.

Program and erase properties of a memory cell are a function of a gatecoupling ratio, which is a function of a capacitance between the FG andthe CG of a memory cell. With a device 300 or 400 that includes a planarnitride structure 304, such as shown in the FIGS. 3E-3K and 4E, thecapacitance created between the IGD and the FG may be reduced oreliminated, such as to make the capacitance a function of the distancebetween a surface of the FG 302 and an opposing surface of the CG 306.Such a configuration may reduce the sources of variation in the gatecoupling ratio, such as to improve the uniformity in memory cell programand erase performance. A device with improved FG to CG alignment mayinclude an improved V_(g) or V_(t), such as to help better control achannel formation. Another advantage may include reducing ISPPdegradation issues or maintaining a sufficiently low V_(t), such as byreducing the V_(t) shift caused by cycling by reducing the chargetrapped on the nitride.

The above description and the drawings illustrate some embodiments ofthe invention to enable those skilled in the art to practice theembodiments of the invention. Other embodiments may incorporatestructural, logical, electrical, process, and other changes. Examplesmerely typify possible variations. Portions and features of someembodiments may be included in, or substituted for, those of others.Many other embodiments will be apparent to those of skill in the artupon reading and understanding the above description.

1. (canceled)
 2. A method, comprising: forming an etch stop materialover a substrate; forming alternating conductive tiers and dielectrictiers above the etch stop material; forming a trench extending throughthe alternating conductive tiers and dielectric tiers to the etch stopmaterial; forming polysilicon extending within the trench and contactingthe etch stop material; at least partially oxidizing the polysiliconwithin the trench; and removing at least a portion of the oxidizedpolysilicon contacting the etch stop material.
 3. The method of claim 2,further comprising: recessing the conductive tiers relative to thedielectric tiers to form recesses in which the remaining material of theconductive tiers forms respective memory cell control gates, wherein theformed polysilicon extends within the recesses as well as in contactwith the etch stop material.
 4. The method of claim 3, furthercomprising: forming a nitride material on the at least partiallyoxidized polysilicon; and removing at least a portion of the nitridematerial to form a nitride structure within the recesses.
 5. The methodof claim 2, wherein the etch stop material comprises a metal oxide. 6.The method of claim 5, where the metal oxide is selected from aluminumoxide, zirconium oxide, hafnium oxide, silver oxide, iron oxide,chromium oxide, titanium oxide, copper oxide, and zinc oxide.
 7. Themethod of claim 2, wherein oxidizing the polysilicon within the trenchcomprises performing an in-situ steam generation oxidation process tooxidize exposed polysilicon within the trench.
 8. The method of claim 2,wherein the remaining oxidized polysilicon forms at least part of aninter-poly dielectric layer of a memory cell and contacts at least aportion of the etch stop material.
 9. The method of claim 8, furthercomprising: recessing the conductive tiers relative to the dielectrictiers to form recesses in which the remaining material of the conductivetiers forms respective memory cell control gates; wherein the formedpolysilicon extends within the recesses as well as in contact with theetch stop material.
 10. The method of claim 9, further comprising:forming a nitride material on the at least partially oxidizedpolysilicon; and removing at least a portion of the nitride material toform nitride structures within the recesses, wherein the oxidizedpolysilicon protects the etch stop layer from damage during the removalof the nitride material.
 11. The method of claim 10, wherein the etchstop layer is metal oxide and removing at least a portion of the nitridematerial comprises performing an acid etch.
 12. The method of claim 11,where the metal oxide is selected from aluminum oxide, zirconium oxide,hafnium oxide, silver oxide, iron oxide, chromium oxide, titanium oxide,copper oxide, and zinc oxide.
 13. The method of claim 10 whereinremoving at least a portion of the nitride material comprises performingan acid etch.
 14. A method, comprising: forming a metal oxide etch stopmaterial over a substrate; forming alternating conductive tiers anddielectric tiers above the metal oxide etch stop material; forming atrench extending vertically through the alternating conductive tiers anddielectric tiers and at least partially into the etch stop material;horizontally recessing the conductive tiers relative to the dielectrictiers to form recesses in which the remaining material of the conductivetiers forms respective memory cell control gates; forming a layer ofpolysilicon extending within the trench and contacting exposed etch stopmaterial within the trench, wherein the formed polysilicon extendswithin the recesses as well as in contact with the etch stop material;at least partially oxidizing the polysilicon within the trench to form alayer of oxidized polysilicon vertically above the exposed etch stoplayer; forming a nitride material on the at least partially oxidizedpolysilicon, wherein the formed nitride material extends within therecesses; removing at least a portion of the nitride material using acidto form a nitride structures within the recesses, wherein the layer ofoxidized polysilicon protects the metal oxide etch stop layer from theacid during the removal of the nitride material; and removing at least aportion of the oxidized polysilicon contacting the metal oxide etch stopmaterial and the underlying metal oxide layer to expose the substrate.15. The method of claim 14 where removing the portion of the nitridematerial uses a hot phosphoric acid.
 16. The method of claim 14, whereinthe remaining oxidized polysilicon within the recesses and the nitridestructures within the recesses form at least part of an inter-polydielectric layer of a memory cell, and wherein the remaining oxidizedpolysilicon extends through the trench to contact at least a portion ofthe etch stop material.
 17. The method of claim 14, where the metaloxide is selected from aluminum oxide, zirconium oxide, hafnium oxide,silver oxide, iron oxide, chromium oxide, titanium oxide, copper oxide,and zinc oxide.
 18. The method of claim 14, wherein oxidizing thepolysilicon within the trench comprises performing an in-situ steamgeneration oxidation process to oxidize exposed polysilicon within thetrench.